Analog and Digital Design FPGA, DSP, PLL, and Embedded Firmware SMP and Distributed Multiprocessing ASIC Reference Design and Documentation

Analog and Digital Design and Simulation

• High Speed FPGA Design and Simulation
• SPICE simulation and test (1MHz to 5GHz)
• PCAD PCBA layout for high speed Surface Mount circuitry
• Discrete Analog design, including PLL and Servo Systems

Reference Design and Documentation

• Design of Reference circuit boards for ASIC circuits or Microprocessors
• Experience with extremely complex debug, including Microprocessor Logic debug
• Communications skills to accurately describe even the most complex ASIC design

Surface Mount, BGA, ASIC and MMIC Components Surface mount Protoype and Assembly equipment, including "Chipmaster" Machine for Automatic reflow of Ball Grid Array (BGA) ASIC and MMIC packages with inbuilt vacuum-operated component handling Vacuum operated manual pick and place for miniature SM components Wide range of Prototype Surface Mount Resistors, Capacitors and Semiconductors Solder Paste dispenser with controlled drop size

Phase Locked Loop Design

• Microprocessor and DSP based Digital PLL design, simulation, and verification
• Servo Loop and Servo System design and simulation
• Analog PLL design, SPICE simulation, and verification

Test Equipment

• Test and characterization performed with my equipment, or with yours
• 200MHz, 80 Channel Logic Analyser, Digital and Analog Scopes, Spectrum Analyzers, Sweep Generators, Synthesizers, frequency and pulse counters.

Click here for a list of articles written for the E.E.Times CMP Publishing Group

Click here for a general list of publications on Analog, Digital and Software Design

DISCLAIMER: Any resemblance between the above views and those of my employer(s) are purely coincidental. Any resemblance between the above and my own views is non-deterministic. My existence can be challenged. The question of the existence of views in the absence of anyone to hold them is left as an exercise for the reader. The question of the existence of the reader is left as an exercise in the second order coefficient.